Why do dynamic Rams need constant refreshing?
Why refresh?
DRAM uses capacitors as storage cells. These capacitors, being really small and made from silicon, will leak off their voltage over time. That’s the D in DRAM: the cells are dynamic: their charge state changes.
To preserve the logic state of those leaky DRAM cells, their state must be read before their charge has bled off, then written back to bring their state to full, freshly-written charge. That’s refresh, in a nutshell.
To help deal with this, DRAMs implement a special kind of read-then-write cycle, called refresh, that hits multiple cells at once and writes them back. Typically, this is one or more rows of cells, about 1/256th of the DRAM at a time.
The host refresh operation is a race against time: all the DRAM rows have to be hit in time before their contents leak away. This usually works out to between 8 and 16ms to hit all the rows.
In contrast, Static RAM, or SRAM, uses a latch as a storage element. The latch keeps its state as long as the power is kept on or it’s written with a new value.
What does this mean with power and density?
SRAM can, in theory, have almost no standby power, as it uses a CMOS latch to store data. In practice, fast SRAM will have fairly high standby leakage current and even higher current during activity due to the use of low-threshold transistors to increase speed.
SRAM latches take between 4 and 8 transistors per bit, and all of them can leak.
Meanwhile, DRAM has standby power to deal with refreshes. There’s considerable effort by chipmakers to offer low-power self-refresh modes that both stretches out the time between each refresh operation, and doesn’t require host intervention once that mode is entered. This self-refresh mode gets used in computer ‘sleep’ state, allowing CPU power-down yet enabling near-instant wake up time.
Density-wise, DRAM basically uses one transistor per cell, connecting to the capacitor which is dug vertically as a well into the silicon. This makes DRAM area per bit very small compared to the SRAM 6T or 8T latch cell. With fewer transistors, DRAM standby leakage per bit is also reduced.
So overall, owing to its density and lower transistor count per bit, DRAM is substantially better power than fast SRAM; but substantially worse than slow, low-leakage SRAM because it requires refreshing.
How DRAM refresh works
While the memory is operating, each memory cell must be refreshed repetitively, within the maximum interval between refreshes specified by the manufacturer, which is usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses.
The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation, the sense amplifiers after reading and latching the data, rewrite the data in the accessed row before sending the bit from a single column to output. This means the normal read electronics on the chip can refresh an entire row of memory in parallel, significantly speeding up the refresh process. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time an abbreviated cycle called a refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons:
- For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits.
- Data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU.
The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed.
Types of refresh circuits
Although in some early systems the microprocessor controlled refresh, with a timer triggering a periodic interrupt that ran a subroutine that performed the refresh, this meant the microprocessor could not be paused, single-stepped, or put into energy-saving hibernation without stopping the refresh process and losing the data in memory. So in modern systems refresh is handled by circuits in the memory controller, which may be embedded in the chip itself. Some DRAM chips, such as pseudostatic RAM (PSRAM), have all the refresh circuitry on the chip, and function like static RAM as far as the rest of the computer is concerned.
Usually the refresh circuitry consists of a refresh counter which contains the address of the row to be refreshed which is applied to the chip's row address lines, and a timer that increments the counter to step through the rows. This counter may be part of the memory controller circuitry, or on the memory chip itself. Two scheduling strategies have been used:
- Burst refresh - a series of refresh cycles are performed one after another until all the rows have been refreshed, after which normal memory accesses occur until the next refresh is required
- Distributed refresh - refresh cycles are performed at regular intervals, interspersed with memory accesses.
Burst refresh results in long periods when the memory is unavailable, so distributed refresh has been used in most modern systems, particularly in real time systems. In distributed refresh, the interval between refresh cycles is
For example, DDR SDRAM has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs.
Recent generations of DRAM chips contain an integral refresh counter, and the memory control circuitry can either use this counter or provide a row address from an external counter. These chips have three standard ways to provide refresh, selected by different patterns of signals on the "column select" (CAS) and "row select" (RAS) lines:
- "RAS only refresh" - In this mode the address of the row to refresh is provided by the address bus lines, so it is used with external counters in the memory controller.
- "CAS before RAS refresh" (CBR) - In this mode the on-chip counter keeps track of the row to be refreshed and the external circuit merely initiates the refresh cycles.[5] This mode uses less power because the memory address bus buffers don't have to be powered up. It is used in most modern computers.
- "Hidden refresh" - This is an alternate version of the CBR refresh cycle which can be combined with a preceding read or write cycle.[5] The refresh is done in parallel during the data transfer, saving time.
Since the 2012 generation of DRAM chips, the "RAS only" mode has been eliminated, and the internal counter is used to generate refresh. The chip has an additional sleep mode, for use when the computer is in sleep mode, in which an on-chip oscillator generates internal refresh cycles so that the external clock can be shut down.
Refresh overhead
The fraction of time the memory spends on refresh, the refresh overhead, can be calculated from the system timing:
For example, an SDRAM chip has 213 = 8,192 rows, a refresh interval of 64 ms, the memory bus runs at 133 MHz, and the refresh cycle takes 4 clock cycles. The time for a refresh cycle is
So less than 0.4% of the memory chip's time will be taken by refresh cycles. In SDRAM chips, the memory in each chip is divided into banks which are refreshed in parallel, saving further time. So the number of refresh cycles needed is the number of rows in a single bank, given in the specifications, which in the 2012 generation of chips has been frozen at 8,192.
Refresh interval
The maximum time interval between refresh operations is standardized by JEDEC for each DRAM technology, and is specified in the manufacturer's chip specifications. It is usually in the range of milliseconds for DRAM and microseconds for eDRAM. For DDR2 SDRAM chips it is 64 ms. It depends on the ratio of charge stored in the memory cell capacitors to leakage currents. Despite the fact that the geometry of the capacitors has been shrinking with each new generation of memory chips, so later generation capacitors store less charge, refresh times for DRAM have been improving; from 8 ms for 1M chips, 32 ms for 16M chips, to 64 ms for 256M chips. This improvement is achieved mainly by developing transistors that cause significantly less leakage. Longer refresh time means a smaller fraction of the device's time is occupied with refresh, leaving more time for memory accesses. Although refresh overhead occupied up to 10% of chip time in earlier DRAMs, in modern chips this fraction is less than 1%.
Because the leakage currents in semiconductors increase with temperature, refresh times must be decreased at high temperature. DDR2 SDRAM chips have a temperature-compensated refresh structure; refresh cycle time must be halved when chip case temperature exceeds 85 °C (185 °F).
The actual persistence of readable charge values and thus data in most DRAM memory cells is much longer than the refresh time, up to 1–10 seconds. However transistor leakage currents vary widely between different memory cells on the same chip due to process variation. In order to make sure that all the memory cells are refreshed before a single bit is lost, manufacturers must set their refresh times conservatively short.
This frequent DRAM refresh consumes a third of the total power drawn by low-power electronics devices in standby mode. Researchers have proposed several approaches for extending battery run-time between charges by reducing the refresh rate, including temperature-compensated refresh (TCR) and retention-aware placement in DRAM (RAPID). Experiments show that in a typical off-the-shelf DRAM chip, only a few weak cells really require the worst-case 64 ms refresh interval,[13] and even then only at the high end of its specified temperature range. At room temperature (e.g. 24 °C (75 °F)), those same weak cells need to be refreshed once every 500 ms for correct operation. If the system can avoid using the weakest 1% of pages, a typical DRAM only needs to be refreshed once a second, even at 70 °C (158 °F), for correct operation of the remaining 99% of the pages. Some experiments combine these two complementary techniques, giving correct operation at room temperature at refresh intervals of 10 seconds.[13]
For error-tolerant applications (e.g. graphics applications), refreshing non-critical data stored in DRAM or eDRAM at a rate lower than their retention period saves energy with minor quality loss, which is an example of approximate computing.
Tirthankar Pal
MBA from IIT Kharagpur with GATE, GMAT, IIT Kharagpur Written Test, and Interview
2 year PGDM (E-Business) from Welingkar, Mumbai
4 years of Bachelor of Science (Hons) in Computer Science from the National Institute of Electronics and Information Technology
Google and Hubspot Certification
Brain Bench Certification in C++, VC++, Data Structure and Project Management
10 years of Experience in Software Development out of that 6 years 8 months in Wipro
Selected in Six World Class UK Universities:-
King's College London, Durham University, University of Exeter, University of Sheffield, University of Newcastle, University of Leeds
