Distinguish between synchronous and asynchronous DRAMS
The key difference between synchronous and asynchronous DRAM is that the synchronous DRAM uses the system clock to coordinate the memory access while asynchronous DRAM does not use the system clock to coordinate the memory access.
The computer memory stores data and instructions. There are mainly two types of memory called RAM and ROM. RAM stands for Random Access Memory while ROM stands for Read Only Memory. The RAM further divides into static RAM and dynamic RAM. This article discusses two types of dynamic RAM namely, synchronous and asynchronous DRAM.
CONTENTS
1. Overview and Key Difference
2. What is Synchronous DRAM
3. What is Asynchronous DRAM
4. Side by Side Comparison – Synchronous vs Asynchronous DRAM in Tabular Form
5. Summary
What is Synchronous DRAM?
RAM is a volatile memory. In other words, the data and instructions written to the RAM are not permanent. Therefore, the data will erase when power off the computer. It is possible to perform both read and write operations in RAM. Moreover, it is fast and expensive. There are two types of RAM. They are the Static RAM (SRAM) and Dynamic RAM (DRAM). The SRAM requires a constant flow of power to retain data while DRAM requires constant refreshes to retain data. Synchronous DRAM and Asynchronous DRAM are two types of DRAM.
Figure 01: SDRAM
In Synchronous DRAM, the system clock coordinates or synchronizes the memory accessing. Therefore, the CPU knows the timing or the exact number of cycles in which the data will be available from the RAM to the input, output bus. It increases memory read and write speed. Overall, the Synchronous DRAM is faster in speed and operates efficiently than the normal DRAM.
What is Asynchronous DRAM?
The first personal computers used asynchronous DRAM. It is an older version of DRAM. In asynchronous DRAM, the system clock does not coordinate or synchronizes the memory accessing. When accessing the memory, the value appears on the input, output bus after a certain period. Therefore, it has some latency that minimizes the speed.
Usually, asynchronous RAM works in low-speed memory systems but not appropriate for modern high-speed memory systems. At present, the manufacturing of asynchronous RAM is quite low. Today, synchronous DRAM is used instead of the asynchronous DRAM.
What is the Difference Between Synchronous and Asynchronous DRAM?
Synchronous DRAM uses a system clock to coordinate memory accessing while Asynchronous DRAM does not use a system clock to synchronize or coordinate memory accessing. Synchronous DRAM is faster and efficient then asynchronous DRAM.
Furthermore, synchronous DRAM provides high performance and better control than the asynchronous DRAM. Modern high-speed PCs uses synchronous DRAM while older low-speed PCs used asynchronous DRAM.
Summary – Synchronous vs Asynchronous DRAM
The difference between synchronous and asynchronous DRAM is that synchronous DRAM uses the system clock to coordinate the memory access while asynchronous DRAM does not use the system clock to coordinate the memory accessing. In brief, the synchronous DRAM provides better control and high performance than the asynchronous DRAM.
Bus transactions on PCI
Let's look at what happens during a PCI data transfer or bus transaction. First, the initiating device has to get permission to have control of the bus. This is determined during the process of bus arbitration. A function called the arbiter, which is part of the PCI chip set, decides which device is allowed to initiate a transaction next. The arbiter uses an algorithm designed to avoid deadlocks and prevent one or more devices from monopolising the bus to the exclusion of others.
Having gained control of the bus, an initiator then places the target address and a code representing the transfer type on the bus. Other PCI devices determine, by decoding the address and the command type information, whether they are the intended target for the transfer. The target device claims the transaction by asserting a device select signal.
Once the target has sent its acknowledgement, the bus transaction enters the data phase. During this phase the data is transferred. The transfer can be terminated either by the initiator, when the transfer is completed or when its permission to use the bus is withdrawn by the arbiter, or by the target if it is unable to accept any more data for the time being. If the latter, the transfer must be restarted as a separate transaction. One of the rules of PCI protocol is that a target must terminate a transaction and release the bus if it is unable to process any more data, so a slow target device cannot hog the bus and prevent others from using it.
Note that although all PCI data transfers are burst transfers, a device does not have to be able to accept long bursts of data. A target device can terminate the data phase after one cycle if it wants to. Such behaviour would be perfectly acceptable in a non-performance-critical device. Even high performance devices may have to terminate a burst, since their data buffers will be of finite size and if they cannot process the data as quickly as it is sent these buffers will eventually fill up.
Tirthankar Pal
MBA from IIT Kharagpur with GATE, GMAT, IIT Kharagpur Written Test, and Interview
2 year PGDM (E-Business) from Welingkar, Mumbai
4 years of Bachelor of Science (Hons) in Computer Science from the National Institute of Electronics and Information Technology
Google and Hubspot Certification
Brain Bench Certification in C++, VC++, Data Structure and Project Management
10 years of Experience in Software Development out of that 6 years 8 months in Wipro
Selected in Six World Class UK Universities:-
King's College London, Durham University, University of Exeter, University of Sheffield, University of Newcastle, University of Leeds
No comments:
Post a Comment