Computer Organization and Architecture (Solved Answers from QBank - VII) - Tirthankar Pal - MBA from IIT Kharagpur, GATE, GMAT, IIT Written Test, Interview were a part of MBA Entrance, B.S. in Computer Science from NIELIT

Direct Memory Access (DMA) :

DMA Controller is a hardware device that allows I/O devices to directly access memory with less participation of the processor. DMA controller needs the same old circuits of an interface to communicate with the CPU and Input/Output devices. 

Fig-1 below shows the block diagram of the DMA controller. The unit communicates with the CPU through data bus and control lines. Through the use of the address bus and allowing the DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. RD and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the memory.

DMA controller registers :

The DMA controller has three registers as follows.

• Address register – It contains the address to specify the desired location in memory.
• Word count register – It contains the number of words to be transferred.
• Control register – It specifies the transfer mode.

Note – 

All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can both read and write into the DMA registers under program control via the data bus.

Fig 1- Block Diagram

Explanation :

The CPU initializes the DMA by sending the given information through the data bus.

• The starting address of the memory block where the data is available (to read) or where data are to be stored (to write).
• It also sends word count which is the number of words in the memory block to be read or write.
• Control to define the mode of transfer such as read or write.
• A control to begin the DMA transfer.

Burst Mode –

• In this mode Burst of data (entire data or burst of block containing data) is transferred before CPU takes control of the buses back from DMAC.
• This is the quickest mode of DMA Transfer since at once a huge amount of data is being transferred.
• Since at once only the huge amount of data is being transferred so time will be saved in huge amount.

Percentage of Time CPU remains blocked :
Let time taken to prepare the data be Tx and time taken to transfer the data be Ty. Then percentage of time CPU remains blocked due to DMA is as follows.

Percentage of time CPU remains in blocked state = Ty * 100% / Tx + Ty

Tirthankar Pal
MBA from IIT Kharagpur with GATE, GMAT, IIT Kharagpur Written Test, and Interview
2 year PGDM (E-Business) from Welingkar, Mumbai
4 years of Bachelor of Science (Hons) in Computer Science from the National Institute of Electronics and Information Technology
Google and Hubspot Certification
Brain Bench Certification in C++, VC++, Data Structure and Project Management
10 years of Experience in Software Development out of that 6 years 8 months in Wipro
Selected in Six World Class UK Universities:-
King's College London, Durham University, University of Exeter, University of Sheffield, University of Newcastle, University of Leeds